As a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates electric charge, a complementary metal oxide semiconductor (CMOS) image sensor has been put to practical use. The CMOS image sensor has been widely applied as a part of various electronic apparatuses such as a digital camera, a video camera, a surveillance camera, a medical endoscope, a personal computer (PC), a portable terminal device (mobile device) such as a mobile phone, etc.
The CMOS image sensor has a floating diffusion (FD) amplifier including a photodiode (photoelectric conversion element) and an FD for each pixel. In the readout, a column parallel output type in which one row in a pixel array is selected and simultaneously read in a column output direction is the mainstream.
FIG. 1 is a diagram illustrating a configuration example of a pixel part and a vertical scanning circuit of a general column parallel output type solid-state imaging device (CMOS image sensor).
In a solid-state imaging device 1 of FIG. 1, a pixel part 2 in which pixels PXL are arranged in a matrix, and a vertical scanning circuit (row scanning circuit) 3 for driving the pixels through a row scanning control line in a shutter row and a reading row are illustrated. FIG. 1 illustrates a pixel array of one row.
Basically, for example, for one photodiode PD, each of the pixels PXL of the pixel part 2 includes, as active elements, four elements corresponding to a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element (amplifying element), and a selection transistor SEL-Tr as a selection element.
The transfer transistor TG-Tr is held in a non-conductive state during a charge storage period of the photodiode PD, and is held in a conductive state by a drive control signal DTG applied to a gate through a control signal line LTG to transfer electric charge photo-electrically converted by the photodiode PD to a floating diffusion FD in a transfer duration in which stored electric charge of the photodiode PD are transferred to the floating diffusion FD.
The reset transistor RST-Tr resets a potential of the floating diffusion FD to a potential VDD of a power supply line when a drive control signal (reset signal) DRST is applied to a gate thereof through a control signal line LRST.
A gate of the source follower transistor SF-Tr is connected to the floating diffusion FD. The source follower transistor SF-Tr is connected to a vertical signal line LSGN through the select transistor SEL-Tr, and is included in a source follower and a constant current source of a load circuit outside the pixel part. Further, a drive control signal (address signal or select signal) DSEL is applied to a gate of the selection transistor SEL-Tr through the control signal line LSEL to turn on the selection transistor SEL-Tr. When the select transistor SEL-Tr is turned on, the source follower transistor SF-Tr amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line LSGN. A voltage output from each of the pixels PXL is output to a column parallel processing part as a pixel signal reading circuit through the vertical signal line LSGN. In column parallel processing, image data is converted, for example, from an analog signal to a digital signal and transferred to a signal processing part in a subsequent stage, where predetermined image signal processing is performed to obtain a desired image.
As illustrated in FIG. 1, a vertical scanning circuit 3 includes a row driver 31 that applies a drive control signal DTG (DRST, DSEL) at a level of a positive power-source voltage to a corresponding control signal line LTG (LRST, LSEL) upon reception of a control signal TG (RST, SEL), and a voltage supply part 32 that supplies a voltage different from a positive power-source voltage vaa, for example, a voltage higher than or equal to the positive power-source voltage vaa to a driver. The voltage supply part 32 includes an operational amplifier (Op Amp) OPA32, a capacitor bridge circuit CB32 including an internal capacitor Cbst having an internal capacitance of about 100 pF, switches SW (1 to 4), etc., and an external capacitor Cext having a capacitance of about 10 nF.
Incidentally, in the CMOS image sensor as a solid-state imaging device 10, an operation of successively scanning and reading photocharge generated and stored by the photodiode for each pixel or for each row is performed. In the case of this successive scanning, that is, when a rolling shutter is employed as an electronic shutter, it is impossible to set the same start time and end time of exposure for storing the photocharge for all pixels. For this reason, in the case of successive scanning, there is a problem that distortion occurs in a captured image when capturing a moving subject.
Therefore, in use for imaging of a subject moving at high speed which may not tolerate image distortion, or sensing that requires simultaneousness of captured images, a global shutter that executes exposure start and exposure end at the same timing for all pixels in a pixel array part is employed as the electronic shutter.
In a CMOS image sensor adopting the global shutter as the electronic shutter, for example, a signal holding part that holds a signal read from a photoelectric conversion reading part in a signal holding capacitor is provided in a pixel. In the CMOS image sensor adopting the global shutter, electric charges are stored as voltage signals from the photodiode all at once in the signal holding capacitor of the signal holding part, and then successively read to ensure simultaneousness of the entire image (for example, see J. Aoki, et al., “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with −160 dB Parasitic Light Sensitivity In-Pixel Storage Node” ISSCC 2013/SESSION 27/IMAGE SENSORS/27.3.).
The vertical scanning circuit 3 including the voltage supply part 32 and the row driver 31 of the CMOS image sensor with a rolling shutter operation needs to drive only one row of a pixel array. In the conventional voltage supply part 32, the operational amplifier OPA32 is used to charge the capacitor Cbst in a chip with a desired reference voltage vref, and generate a power-source voltage corresponding to an overvoltage or undervoltage by pumping up using the power-source voltage vaa. Then, subsequently, electric charge is transferred to the external capacitor Cext a plurality of times.
However, in order to charge the internal capacitor Cbst and the external capacitor Cext within a required time, it is necessary to increase the area and power of the operational amplifier OPA32 since a large slew rate and high-speed response are required.
In addition, a booster of the vertical scanning circuit 3 of the CMOS image sensor with the global shutter operation needs to drive the entire pixel array of the pixel part 2, and thus the load capacity is significantly large. For example, the load capacity is about 1,000 times the load capacity of the rolling shutter operation. In the case of using a booster having the same configuration as that of a CMOS image sensor having a rolling shutter function, a charge up time needs to be multiplied by 1,000 times. Alternatively, the capacitance of the internal capacitor Cbst needs to be under 1,000×. Alternatively, the operating speed (charge and transfer cycle) needs to be under 1,000×.
Of these conditions, in order to satisfy the conditions of the capacity and the operating speed of the internal capacitor Cbst, the operational amplifier OPA32 needs to have a significantly large slew rate. Therefore, at present, it is significantly difficult to design a voltage supply part (booster) of the CMOS image sensor having the global shutter function on a silicon substrate.